1. Field of Invention
The present invention is related to semiconductor memory and in particular to testing memory bit lines in an IC test.
2. Description of Related Art
The testing of integrated circuits and in particular semiconductor memory chips presents a challenge to detect defects that prevent proper operation of the memory chips. Bit lines connecting columns of memory cells are orthogonal to word lines connecting rows of the memory cells. At each crossing of the bit lines and the word lines there is an opportunity for defects located at the crossing to produce a leakage current between the word lines and the bit lines. A method for detecting the leakage current entails using sense amplifiers connected to the bit lines. In order to allow the sense amplifiers to measure the leakage requires a time delay to allow the leakage current to charge the bit line capacitance. An RC (resistor capacitor) network is integrated into the memory chip to allow the memory chip for the purpose of providing sufficient time delay to permit the charging of the bit line capacitance so that the sense amplifiers can measure the defect. The capacitor of the RC network used only in test mode is relatively large and affects the size of the memory chip.
In U.S. Pat. No. 6,826,079 (Tran) a method and system is directed to minimizing leakage current within an array of memory cells in which a differential sense amplifier differentiates the sensed current from a read operation from a reference value. U.S. Pat. No. 6,639,861 (Stief et al.) is directed to using a control circuit to switch to a non-conducting state in which the leakage behavior of a bit line can be read out during read out of a data signal. In U.S. Pat. No. 6,118,713 (Raad) a memory stress test is directed to writing a logic bit in a weakened state whereby the logic bit is read back out to stress the memory and identify weak sense amplifiers and memory cells. U.S. Pat. No. 5,894,445 (Kobyashi), is directed to a semiconductor memory in which a bit line control circuit reads data from a cell to detect faults.
In FIG. 1 is shown a signal diagram of prior art for the normal activation of a memory chip to read data from memory cells. At a constant time delay T1 after a row-active command (ACT) a word line WL is turned on. Upon turning on the word line the differential voltage ΔVBL,BLB between the bit line BL and bit line bar BLB begins to be established. After a constant time delay T2 the bit line sense amplifier BLSA is turned on, and the bit line BL and bit line bar BLB are read by the bit line sense amplifier. The delay times T1 and T2 are relatively short having similar value and created by an on-chip RC network. When the word line is turned off a precharge command PRCH is issued to precharge the bit lines and the bit lines return to a quiescent state.
FIG. 2 shows a signal diagram of prior art where a time delay T3 is used during chip and module test to delay turning on the bit line sense amplifier BLSA. The time delay T3 is long and requires a large capacitor in an RC network, which occupies a considerable amount of the semiconductor memory chip real estate. The length of the time delay is established to allow leakage from defects to charge the bit lines BL and BLB sufficiently to allow a measurement of the leakage by the bit line sense amplifier BLSA. The size of the capacitor necessary to produce the time delay T3 is large and substantially increases the size of the memory chip.